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  1. RISC-V CPU with FPGA
RISC-V CPU with FPGA RISC-V CPU with FPGA

RISC-V CPU with FPGA

03 Nov 2025 / 1 minute to read / Categories: Featured, Academic

WORK IN PROGRESS

This project page is heavily a WIP, but publishing it first to pressure myself to finish it ASAP!

TLDR Summary

Designed a 5-stage pipelined RISC-V CPU with support for RV32IM instruction set. Added enhancements like hazard detection and forwarding, 2-bit branch prediction, and vectored interrupt handling. Written in Verilog and implemented on a Nexys4 FPGA board.

This project was built up over the course of 8 weeks for the module CG3207: Computer Architecture. This module went in depth into the design of a CPU, covering many key topics like its microarchitecture, advanced pipelining techniques, memory management, exception handling, and so on.

The final CPU design was the result of progressive lab assignments that culminated in a 5-stage pipelined RISC-V CPU supporting the RV32IM instruction set, with enhancements beyond these basic requirements being open-ended. The CPU was written in Verilog and implemented on a Nexys4 DDR FPGA board.

The following sections detail the CPU’s design, as well as the enhancements my group (pair) implemented.

<TODO: get those sections doneeee>

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